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? semiconductor components industries, llc, 2001 february, 2001 rev. 3 1 publication order number: mc33762/d mc33762 dual ultra low-noise low dropout voltage regulator with 1.0 v on/off control the mc33762 is a dual low dropout (ldo) regulator featuring excellent noise performances. thanks to its innovative design, the circuit reaches an impressive 40 m vrms noise level without an external bypass capacitor. housed in a small m 8 package, it represents the ideal designer's choice when space and noise are at premium. the absence of external bandgap capacitor accelerates the response time to a wakeup signal and keeps it within 40 m s, making the mc33762 as a natural candidate for portable applications. the mc33762 also hosts a novel architecture which prevents excessive undershoots in the presence of fast transient bursts, as in any bursting systems. finally, with a static line regulation better than 75 db, it naturally shields the downstream electronics from choppy lines. features ? nominal output current of 80 ma with a 100 ma peak capability ? ultralow noise: 150 nv/ hz @ 100 hz, 40 m vrms 100 hz100 khz typical, i out = 60 ma, co = 1.0 m f ? fast response time from off to on: 40 m s typical ? ready for 1.0 v platforms: on with a 900 mv high level ? typical dropout of 90 mv @ 30 ma, 160 mv @ 80 ma ? ripple rejection: 70 db @ 1.0 khz ? 1.5% output precision @ 25 c ? thermal shutdown ? v out available at 2.5 v, 2.8 v, and 3.0 v ? separate dice for each regulator provides maximum isolation between regulators ? operating range from 40 to +85 c applications ? noise sensitive circuits: vcos rf stages, etc. ? bursting systems (tdma phones) ? all battery operated devices 1 http://onsemi.com 8 micro8 dm suffix case 846a pin configuration and marking diagram 1 2 3 4 8 7 6 5 gnd1 en1 gnd2 en2 v out1 v cc1 v out2 v cc2 see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information 762 yww (top view) y = year ww = work week
mc33762 http://onsemi.com 2 thermal shutdown on/off band gap reference *current limit *antisaturation protection *load transient improvement v out v cc1 gnd1 8 7 1 2 thermal shutdown on/off band gap reference *current limit *antisaturation protection *load transient improvement v out v cc2 gnd2 en2 6 5 3 4 en1 figure 1. simplified block diagram pin function descriptions pin # pin name function description 1 gnd1 ground of the 1st ldo 2 en1 enables the 1st ldo a 900 mv level on this pin is sufficient to start this ldo. a 150 mv shuts it down. 3 gnd2 ground of the 2nd ldo 4 en2 enables the 2nd ldo a 900 mv level on this pin is sufficient to start this ldo. a 150 mv shuts it down. 5 v cc2 2nd ldo v cc pin this pin brings the power to the 1st ldo and requires adequate decoupling. 6 v out2 shuts or wakesup the ic this pin requires a 1.0 m f output capacitor to be stable. 7 v cc1 1st ldo v cc pin this pin brings the power to the 1st ldo and requires adequate decoupling. 8 v out1 delivers the output voltage this pin requires a 1.0 m f output capacitor to be stable. maximum ratings value rating pin # symbol min max unit power supply voltage 1 v in 12 v esd capability, hbm model all pins 1.0 kv esd capability, machine model all pins 200 v maximum power dissipation nw suffix, plastic package thermal resistance junctiontoair p d r ja internally limited 240 w c/w operating ambient temperature maximum junction temperature (note 1.) maximum operating junction temperature (note 2.) t a t jmax t j 40 to +85 150 125 c c c storage temperature range t stg 60 to +150 c 1. internally limited by shutdown. 2. specifications are guaranteed below this value.
mc33762 http://onsemi.com 3 electrical characteristics (for typical values t a = 25 c, for min/max values t a = 40 c to +85 c, max t j = 125 c unless otherwise noted) characteristics pin # symbol min typ max unit logic control specifications input voltage range 24 v on/off 0 v in v on/off input resistance (all versions) 24 r on/off 250 k on/off control voltages (note 3.) logic zero, off state, i o = 50 ma logic one, on state, i o = 50 ma 24 v on/off 900 150 mv currents parameters current consumption in off state (all versions) off mode current: v in = v out + 1.0 v, i o = 0, v off = 150 mv iq off 0.1 2.0 a current consumption in on state (all versions) on mode current: v in = v out + 1.0 v, i o = 0, v on = 3.5 v iq on 180 a current consumption in on state (all versions), on mode saturation current: v in = v out 0.5 v, no output load iq sat 800 a current limit v in = vout nom + 1.0 v, output is brought to vout nom 0.3 v (all versions) i max 100 180 ma output voltages v out + 1.0 v < v in < 6.0 v, t a = 25 c, 1.0 ma < i out < 80 ma 2.5 v 57 v out 2.462 2.5 2.537 v 2.8 v 57 v out 2.758 2.8 2.842 v 3.0 v 57 v out 2.955 3.0 3.045 v 3.3 v 57 v out 3.250 3.3 3.349 v 3.6 v 57 v out 3.546 3.6 3.654 v other voltages up to 5.0 v available in 50 mv increment steps 57 v out 1.5 x +1.5 % v out + 1.0 v < v in < 6.0 v, t a = 40 c to +85 c, 1.0 ma < i out < 80 ma 2.5 v 57 v out 2.425 2.5 2.575 v 2.8 v 57 v out 2.716 2.8 2.884 v 3.0 v 57 v out 2.91 3.0 3.090 v 3.3 v 57 v out 3.201 3.3 3.399 v 3.6 v 57 v out 3.492 3.6 3.708 v other voltages up to 5.0 v available in 50 mv increment steps 57 v out 3.0 x +3.0 % line and load regulation, dropout voltages line regulation (all versions) v out + 1.0 v < v in < 12 v, i out = 80 ma 57 reg line 20 mv load regulation (all versions) v in = v out + 1.0 v, c out = 1.0 f, i out = 1.0 to 80 ma 57 reg load 40 mv dropout voltage (all versions) (note 3.) i out = 30 ma i out = 60 ma i out = 80 ma 57 57 57 v in v out v in v out v in v out 90 140 160 150 200 250 mv 3. voltage slope should be greater than 2.0 mv/ s
mc33762 http://onsemi.com 4 electrical characteristics (continued) (for typical values t a = 25 c, for min/max values t a = 40 c to +85 c, max t j = 125 c unless otherwise noted) characteristics pin # symbol min typ max unit dynamic parameters ripple rejection (all versions) v in = v out + 1.0 v + 1.0 khz 100 mvpp sinusoidal signal 57 ripple 70 db output noise density @ 1.0 khz 57 150 nv/ hz rms output noise voltage (all versions) c out = 1.0 f, i out = 50 ma, f = 100 hz to 1.0 mhz 57 noise 35 v output rise time (all versions) c out = 1.0 f, i out = 50 ma, 10% of rising on signal to 90% of nominal v out 57 t rise 40 s thermal shutdown thermal shutdown (all versions) 125 c
mc33762 http://onsemi.com 5 definitions load regulation the change in output voltage for a change in output current at a constant chip temperature. dropout voltage the input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. measured when the output drops 100 mv below its nominal value (which is measured at 1.0 v differential value). the dropout level is affected by the chip temperature, load current and minimum input supply requirements. output noise voltage this is the integrated value of the output noise over a specified frequency range. input voltage and output current are kept constant during the measurement. results are expressed in m vrms. maximum power dissipation the maximum total dissipation for which the regulator will operate within its specs. quiescent current the quiescent current is the current which flows through the ground when the ldo operates without a load on its output: internal ic operation, bias etc. when the ldo becomes loaded, this term is called the ground current. it is actually the difference between the input current (measured through the ldo input pin) and the output current. line regulation the change in output voltage for a change in input voltage. the measurement is made under conditions of low dissipation or by using pulse technique such that the average chip temperature is not significantly affected. one usually distinguishes static line regulation or dc line regulation (a dc step in the input voltage generates a corresponding step in the output voltage) from ripple rejection or audio susceptibility where the input is combined with a frequency generator to sweep from a few hertz up to a defined boundary while the output amplitude is monitored. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated at typically 125 c, the regulator turns off. this feature is provided to prevent catastrophic failures from accidental overheating. maximum package power dissipation the maximum power package power dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125 c. depending on the ambient temperature, it is possible to calculate the maximum power dissipation and thus the maximum available output current.
mc33762 http://onsemi.com 6 characterization curves curves are common to both regulators 25 c 40 c 25 c 85 c figure 2. ground current versus output current figure 3. quiescent current versus temperature figure 4. dropout versus output current figure 5. output voltage versus output current output current (ma) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 100 80 60 0 ground current (ma) ambient temperature ( c) 100 80 60 40 20 0 20 40 60 180 175 170 quiescent current ( a) 165 0.5 0 185 40 20 output current (ma) 200 150 100 50 100 80 60 0 dropout (mv) output current (ma) 100 80 60 40 20 0 2.800 2.795 2.790 output voltage (v) 2.775 0 2.805 40 20 2.785 2.780 figure 6. dropout versus temperature temperature ( c) 180 160 120 100 60 40 100 80 60 60 dropout voltage (mv) 20 0 0 20 80 140 40 40 20 40 c 25 c 85 c 40 c 85 c 40 c 20 c 0 c 1.0 ma 30 ma 60 ma 80 ma
mc33762 http://onsemi.com 7 application hints input decoupling as with any regulator, it is necessary to reduce the dynamic impedance of the supply rail that feeds the component. a 1.0 m f capacitor either ceramic or tantalum is recommended and should be connected close to the mc33762 package. higher values will correspondingly improve the overall line transient response. output decoupling thanks to a novel concept, the mc33762 is a stable component and does not require any specific equivalent series resistance (esr) neither a minimum output current. capacitors exhibiting esrs ranging from a few m up to 3.0 can thus safely be used. the minimum decoupling value is 1.0 m f and can be augmented to fulfill stringent load transient requirements. the regulator accepts ceramic chip capacitors as well as tantalum devices. noise performances unlike other ldos, the mc33762 is a true lownoise regulator. without the need of an external bypass capacitor, it typically reaches the incredible level of 40 m vrms overall noise between 100 hz and 100 khz. to give maximum insight on noise specifications, on semiconductor includes spectral density graphics. the classical bypass capacitor impacts the startup phase of standard ldos. however, thanks to its lownoise architecture, the mc33762 operates without a bypass element and thus offers a typical 40 m s startup phase. protections the mc33762 hosts several protections, giving natural ruggedness and reliability to the products implementing the component. the output current is internally limited to a maximum value of 180 ma typical while temperature shutdown occurs if the die heats up beyond 125 c. these values let you assess the maximum differential voltage the device can sustain at a given output current before its protections come into play. the maximum dissipation the package can handle is given by: p max t jmax t a r ja if t jmax is limited to 125 c, then the mc33762 can dissipate up to 395 mw @ 25 c. the power dissipated by the mc33762 can be calculated from the following formula: ptot v in i gnd (i out ) v in v out i out or vin max ptot v out i out i gnd i out if a 80 ma output current is needed, the ground current is extracted from the datasheet curves: 4.0 ma @ 80 ma. for a half 2.8 v mc33762 (2.8 v) operating at 25 c, the maximum input voltage will then be 7.3 v. typical applications the following picture portrays the typical application of the mc33762.
mc33762 http://onsemi.com 8 figure 7. a typical application schematic mc33762 r1 100 k on/off + c3 1.0 f + c1 1.0 f output 2 input 1 2 3 4 8 7 6 5 r2 100 k on/off + c2 1.0 f output 1 regulator 1 regulator 2 as for any low noise designs, particular care has to be taken when tackling printed circuit board (pcb) layout. connections shall be kept short and wide. layout example as given in the mc33761 application hints can be used as a starting basis.
mc33762 http://onsemi.com 9 understanding the load transient improvement the mc33762 features a novel architecture which allows the user to easily implement the regulator in burst systems where the time between two current shots is kept very small. the quality of the transient response time is related to many parameters, among which the closedloop bandwidth with the corresponding phase margin plays an important role. however, other characteristics also come into play like the series pass transistor saturation. when a current perturbation suddenly appears on the output, e.g. a load increase, the error amplifier reacts and actively biases the pnp transistor. during this reaction time, the ldo is in openloop and the output impedance is rather high. as a result, the voltage brutally drops until the error amplifier effectively closes the loop and corrects the output error. when the load disappears, the opposite phenomenon takes place with a positive overshoot. the problem appears when this overshoot decays down to the ldo steadystate value. during this decreasing phase, the ldo stops the pnp bias and one can consider the ldo asleep (figure 8). if by misfortune a current shot appears, the reaction time is incredibly lengthened and a strong undershoot takes place. this reaction is clearly not acceptable for line sensitive devices, such as vcos or other radiofrequency parts. this problem is dramatically exacerbated when the output current drops to zero rather than a few ma. in this later case, the internal feedback network is the only discharge path, accordingly lengthening the output voltage decay period (figure 9). the mc33762 cures this problem by implementing a clever design where the ldo detects the presence of the overshoot and forces the system to go back to steadystate as soon as possible, ready for the next shot. figure 10 and 11 show how it positively improves the response time and decreases the negative peak voltage. figure 8. a standard ldo behavior when the load current disappears figure 9. a standard ldo behavior when the load current appears in the decay zone figure 10. without load transient improvement figure 11. mc33762 with load transient improvement
mc33762 http://onsemi.com 10 mc33762 has a fast startup phase thanks to the lack of bypass capacitor the mc33762 is able to supply its downstream circuitry as soon as the off to on signal appears. in a standard ldo, the charging time of the external bypass capacitor hampers the response time. a simple solution consists in suppressing this bypass element but, unfortunately, the noise rises to an unacceptable level. mc33762 offers the best of both worlds since it no longer includes a bypass capacitor and starts in less than 40 m s typically (repetitive at 200 hz). it also ensures an incredible lownoise level of 40 m vrms 100 hz100 khz. the following picture details the typical 33762 startup phase. figure 12. repetitive startup waveforms
mc33762 http://onsemi.com 11 typical transient responses figure 13. output is pulsed from 2.0 ma to 80 ma figure 14. discharge effects from 0 to 40 ma figure 15. load transient improvement effect figure 16. load transient improvement effect
mc33762 http://onsemi.com 12 typical transient responses figure 17. mc33762 typical noise density performance figure 18. mc33762 typical ripple rejection performance figure 19. output impedance plot c out = 1.0 f, v in = v out + 1.0 v f, frequency (hz) 0 10 20 30 50 60 70 80 1,000,000 100,000 100 (db) f, frequency (hz) 1,000,000 10,000 1,000 100 2.5 1.0 0.5 z 0 90 100 3.5 10,000 1,000 f, frequency (hz) 100,000 10,000 1,000 100 150 100 50 nv/sqrt hz 0 250 100,000 1.5 2.0 3.0 (ohms) o i o = 1.0 ma 10 ma 20 ma 80 ma 40 i o = 50 ma 10 ma 1,000,000 200 i o = 50 ma 10 ma v in = v o + 1.0 v t a = 25 c c out = 1.0 f v in = v out + 1.0 v t a = 25 c c out = 1.0 f rms noise, i o = 10 ma: 20 hz 100 khz: 29 v 20 hz 1.0 mhz: 31 v rms noise, i o = 50 ma: 20 hz 100 khz: 27 v 20 hz 1.0 mhz: 30 v
mc33762 http://onsemi.com 13 minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will selfalign when subjected to a solder reflow process. mm inches 0.041 1.04 0.208 5.28 0.015 0.38 0.0256 0.65 0.126 3.20
mc33762 http://onsemi.com 14 ordering information part number voltage output package shipping mc33762dm2525r2 2.5 v & 2.5 v micro8 4000 units / tape & reel mc33762dm2828r2 2.8 v & 2.8 v micro8 4000 units / tape & reel mc33762dm3030r2 3.0 v & 3.0 v micro8 4000 units / tape & reel
mc33762 http://onsemi.com 15 package dimensions micro8 plastic package case 846a02 issue e s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l
mc33762 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33762/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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